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slls367d ? june 1999 ? revised august 2007 1 post office box 655303 ? dallas, texas 75265 1.25 gigabits per second (gbps) gigabit ethernet transceiver based on the p802.3z specification transmits serial data up to 1.25 gbps operates with 3.3-v supply voltage 5-v tolerant on ttl inputs interfaces to electrical cables/backplane or optical modules pecl voltage differential signaling load, 1 v typ with 50 ? ? 75 ? receiver differential input voltage 200 mv minimum low power consumption 64-pin quad flat pack with thermally enhanced package description the tnete2201b gigabit ethernet transceiver provides for ultra high-speed bidirectional point-to-point data transmission. this device is based on the timing requirements of the proposed 10-bit interface specification by the p802.3z gigabit task force. 1718 19 rc0 sync gnd_ttl rd0 rd1 rd2 v cc _ttl rd3 rd4 rd5 rd6 v cc _ttl rd7 rd8 rd9 gnd_ttl 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 gnd_cmos td0 td1 td2 v cc _cmos td3 td4 td5 td6 v cc _cmos td7 td8 td9 gnd_cmos gnd_tx tc1 21 22 23 24 din_rxp 63 62 61 60 59 64 58 dout_txp dout_txn gnd_cmos gnd_a reserved lckrefn loopen gnd_a refclk syncen gnd_cmos 56 55 54 57 25 26 27 28 29 53 52 tc0 din_rxn 51 50 49 30 31 32 rbc1 rbc0 gnd_a gnd_rx rc1 gnd_a v cc _tx v cc _a v cc _cmos v cc _a v cc _a v cc _rx v cc _a v cc _a v cc _a v cc _a v cc _a v cc _a phd, pjd, or pjw package (top view) please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications o f texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. copyright ? 1999 ? 2007, texas instruments incorporated
slls367d ? june 1999 ? revised august 2007 2 post office box 655303 ? dallas, texas 75265 description (continued) the intended application of this device is to provide building blocks for developing point-to-point baseband data transmission over controlled-impedance media of approximately 50 ? to 75 ? . the transmission media can be printed-circuit board traces, back planes, cables, or fiber optical media. the ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. the tnete2201b performs the data serialization and deserialization (serdes) functions for the gigabit ethernet physical layer interface. the transceiver operates at 1.25 gbps (typical), providing up to 1000 mbps of bandwidth over a copper or optical media interface. the serializer/transmitter accepts 8b/10b parallel encoded data bytes. the parallel data bytes are serialized and transmitted differentially nonreturn-to-zero (nrz) at pseudo-ecl (pecl) voltage levels. the deserializer/receiver extracts clock information from the input serial stream and deserializes the data, outputting a parallel 10-bit data byte. the 10-bit data bytes are output with respect to two receive byte clocks (rbc0, rbc1), allowing a protocol device to clock the parallel bytes in rbc clock rising edges. the transceiver automatically locks onto incoming data without the need to prelock. however, the transceiver can be commanded to lock to the externally supplied reference clock (refclk) as a reset function, if needed. the tnete2201b provides an internal loopback capability for self-test purposes. serial data from the serializer is passed directly to the deserializer allowing the protocol device a functional self-check of the physical interface. the tnete2201b is characterized for operation from 0 c to 70 c.
slls367d ? june 1999 ? revised august 2007 3 post office box 655303 ? dallas, texas 75265 functional block diagram loopen td0 ? td9 10-bit register 10 / 10 / shift register refclk clock multiplier 2:1 mux synchronous detect syncen sync rd0 ? rd9 10-bit register 10 / 10 / shift register pll clock recovery and data retiming 2 125 mhz 125 mhz 62.5 mhz 62.5 mhz rbc0 rbc1 rx+ rx? tx+ tx?
slls367d ? june 1999 ? revised august 2007 4 post office box 655303 ? dallas, texas 75265 i/o structures _ + v cm v dd v dd 100 ? 4 k ? 4 k ? din_rxp din_rxn v dd v dd dout_txp dout_txn pecl inputs (din_rxp, din_rxn) pecl outputs (din_txp, din_txn) cmos inputs (td0 ? td9, loopen, refclk, syncen, lckrefn) v dd r2 r1 v dd 120 ? input refclk, td0 ? td9 loopen syncen, lckrefn r1 r2 open circuit open circuit open circuit open circuit 400 k ? 400 k ? terminals p n cmos outputs (rd0 ? rd9, rbc0, rbc1, sync) v dd output p n
slls367d ? june 1999 ? revised august 2007 5 post office box 655303 ? dallas, texas 75265 terminal functions terminal description name no. type description i/o and data dout_txp dout_txn 62 61 output differential output transmit. dout_txp and dout_txn are differential serial outputs that interface to a copper or an optical i/f module. these terminals transmit nrz data at a rate of 1.25 gbps. dout_txp and dout_txn are held static when loopen is high and are active when loopen is low. din_rxp din_rxn 54 52 input differential input receive. din_rxp and din_rxn together are the dif ferential serial input interface from a copper or an optical i/f module. these terminals receive nrz data at a rate of 1.25 gbps and are active when loopen is held low. lckrefn 27 input lock to reference. when lckrefn is asserted low, the receive pll phase locks to the supplied refclk signal. lckrefn prelocks or resets the receive pll. loopen 19 input loop enable. when loopen is high (active), the internal loop-back path is activated. the transmitted serial data is directly routed to the inputs of the receiver. this provides a self-test capability in conjunction with the protocol device. the dout_txp and dout_txn outputs are held static during the loop-back test. loopen is held low during standard operational state with external serial outputs and inputs active. rbc0 rbc1 31 30 output receive byte clock. rbc0 and rbc1 are 62.5-mhz recovered clocks used for synchronizing the 10-bit output data on rd0 ? rd9. the 10-bit output data words are valid on the rising edges of rbc0 and rbc1. these clocks are adjusted to half-word boundaries in conjunction with synchronous detect. the clocks are always expanded during data realignment and never slivered or truncated. rbc0 registers bytes 1 and 3 of received data. rbc1 registers bytes 0 and 2 of received data. rc1, rc0 49 48 analog receive capacitor. rc0 and rc1 are external capacitor connections used for the receiver internal pll filter. the recommend value for this external capacitor is 2 nf (a value of 0.1 f can also be used, see note 1). rd0 ? rd9 45,44,43,41 40,39,38,36 35,34 output receive data. these outputs carry 10-bit parallel data output from the transceiver to the protocol layer. the data is referenced to terminals rbc0 and rbc1. received data byte 0, which contains the k28.5 character, is byte aligned to the rising edge of rbc1. rd0 is the first bit received. refclk 22 input reference clock. refclk is an external 125 mhz input clock that synchronizes the receiver and transmitter interfaces. the transmitter uses this clock to register the 10-bit input data (td0..td9) for serialization. refclk is also used as a rx pll preset or reference when lckrefn is enabled. sync 47 output synchronous detect. sync is asserted high upon detection of the k28.5 character in the serial data path. sync is a high level for 1/2 refclk period. sync pulses are output only when syncen is activated (asserted high). note: sync is active on byte0 and, therefore, active on rising edge of rcb1. syncen 24 input synchronous function enable. when syncen is asserted high, the internal synchronization function is activated. when this function is enabled, the transceiver detects the k28.5 character (001 1111010 negative beginning disparity) in the serial data stream and realigns data on byte boundaries if required. when syncen is low, serial input data is unframed in rd0 ? rd9. tc1 tc0 16 17 analog transmit capacitor. tc0 and tc1 are external capacitor connections used for the transmitter internal pll filter. the recommended value of this external capacitor is 2 nf (a value of 0.1 f can also be used, see note 1). td0 ? td9 2,3,4,6 7,8,9,11 12,13 input transmit data. these inputs carry 10-bit parallel data output from a protocol device to the transceiver for serialization and transmission. this 10-bit parallel data is clocked into the transceiver on the rising edge of refclk and transmitted as a serial stream with td0 sent as the first bit. note 1: a filter capacitor value of 0.1 f can be used with the following consideration: the tracking bandwidth of the pll will be reduced due to the larger filter capacitor. this reduces the transmit and receive pll?s ability to reject low-frequency noise or wonder in the voltage supply or datastream. care must be taken in the filtering of the supply v cc _tx (terminal 18) and v cc _rx (terminal 50) to reject power supply noise.
slls367d ? june 1999 ? revised august 2007 6 post office box 655303 ? dallas, texas 75265 terminal functions (continued) terminal description name no. type description power v cc _a 20,28,29,53 55,57,59,60 63 supply analog power. v cc _a provides a supply reference voltage for the high-speed analog circuits. v cc _cmos 5,10,23, supply digital pecl logic power. v cc _cmos provides an isolated low-noise power supply for the logic circuits. v cc _rx 50 supply receiver power. v cc _rx provides a low-noise supply reference voltage for the receiver high-speed analog circuits. v cc _ttl 42,37 supply ttl power. v cc _ttl provides a supply reference voltage for the receiver ttl circuits. v cc _tx 18 supply transmitter power. v cc _tx provides a low-noise supply reference voltage for the transmitter high-speed analog circuits. ground gnd_a 21,32,56,64 ground analog ground. gnd_a provides a ground reference for the high-speed analog circuits. gnd_cmos 1,14, 25,58 ground digital pecl logic ground. gnd_cmos provides an isolated low-noise ground for the logic circuits. gnd_rx 51 ground receiver ground. gnd_rx provides a ground reference for the receiver circuits. gnd_ttl 33,46 ground ttl circuit ground. gnd_ttl provides a ground for ttl interface circuits. gnd_tx 15 ground transmitter ground. gnd_tx provides a ground reference for the transmitter circuits. miscellaneous reserved 26 reserved. internally pulled to gnd, leave open or assert low. detailed description data transmission the transmitter registers incoming 10-bit-wide data words (8b/10b encoded data, td0...td9) on the rising edge of refclk (125 mhz). the reference clock is also used by the serializer, which multiplies the clock by a factor of 10 providing a 1.25 gbaud signal that is fed to the shift register. the data is then transmitted differentially at pecl voltage levels. the 8b/10b encoded data is transmitted sequentially bit 0 through 9. transmission latency the data transmission latency of the tnete2201b is defined as the delay from the initial 10-bit word load to the serial transmission of bit 9. the typical transmission latency is 9 ns. data reception the receiver of the tnete2201b deserializes 1.25 gbps differential serial data. the 8b/10b data (or equivalent) is retimed based on an extracted clock from the serial data. the serial data is then aligned to the 10-bit word boundaries and presented to the protocol controller along with two receive byte clocks (rbc0, rbc1). rbc0 and rbc1 are 180 degrees out of phase and are generated by dividing down the recovered 1.25 gbps (625 mhz) clock by 10 providing for two 62.5-mhz signals. the receiver presents the protocol device byte 0 of the received data valid on the rising edge of rbc1. note: this allows the option of byte alignment without the use of the synchronous detection (sync) function by the protocol device. the receiver pll can lock to the incoming 1.25 ghz data without the need for a lock-to-reference preset. the received serial data rate (rx+ and rx?) should be 1.25 gbps 0.01% (100 ppm) for proper operation.
slls367d ? june 1999 ? revised august 2007 7 post office box 655303 ? dallas, texas 75265 data reception (continued) during a bus error condition or word alignment, the receive byte clocks rbc0 and rbc1 are stretched (never truncated). when the incoming serial data does not meet its frequency requirements, then the receive byte clock frequency is maintained at 62.5 mhz. receive pll operation the receive pll provides automatic locking to the incoming data. at power up, the maximum initial lock time is 500 s. the pll can also be initiated or set to phase lock to the externally supplied reference clock by enabling lock-to-reference (lckrefn). the lock-to-reference causes the receive pll to lock to 10 the reference clock (refclk) input providing a pll preset and reset capability. if during normal operation a transient occurs, which is defined as any arbitrary phase shift in the incoming data and/or a frequency wander of up to 200 ppm, then the pll recovers lock within 2.4 s. any condition exceeding these values is considered a power-up scenario and the pll recovers lock within 500 s with a 0.1 f capacitor the pll recovers lock within 10 ms on power up (see the following note). note: a filter capacitor value of 0.1 f can be used with the following consideration: the tracking bandwidth of the pll will be reduced due to the larger filter capacitor. this reduces the transmit and receive pll?s ability to reject low-frequency noise or wonder in the voltage supply or datastream. care must be taken in the filtering of the supply v cc _tx (terminal 18) and v cc _rx (terminal 50) to reject power supply noise. receiver word alignment the tnete2201b uses a 10-bit k28.5 character (comma character) word alignment scheme. the following sections explain how this scheme works and how it realigns itself. comma character on expected boundary the tnete2201b provides 10-bit k28.5 character recognition and word alignment. the 10-bit word alignment is enabled by forcing sycnen high. this enables the function that examines and compares ten bits of serial input data to the k28.5 synchronization character. the k28.5 character is defined in the fibre channel standard as a pattern consisting of 001 1111010 (a negative number beginning disparity) with the 7 msbs (001 1111) referred to as the comma character. the k28.5 character was implemented specifically for aligning data words. as long as the k28.5 character falls within the expected 10-bit word boundary, the received 10-bit data is properly aligned and data realignment is not required. figure 1 shows the timing characteristics of rbc0, rbc1, sync and rd0 ? rd9 while synchronized. note: the k28.5 character is valid on the rising edge of rbc1. rbc0 rd0 ? rd9 rbc1 sync k28.5 dxx.x dxx.x dxx.x k28.5 dxx.x figure 1. synchronous timing characteristics waveforms
slls367d ? june 1999 ? revised august 2007 8 post office box 655303 ? dallas, texas 75265 comma character not on expected boundary when synchronization is enabled and a k28.5 character straddles the expected 10-bit word boundary, then word realignment is necessary. realignment or shifting the 10-bit word boundary truncates the character following the misaligned k28.5, but the following k28.5 and all subsequent data is aligned properly as shown in figure 2. the 10b specification requires that rclk cycles can not be truncated and can only be stretched or stalled in their current state during realignment. with this design the maximum stretch that occurs is an extra 10 bit times. this occurs during a worst case scenario when the k28.5 is aligned to the falling edge of rbc1 instead of the rising edge. this system transmits a minimum of three consecutively ordered k28.5 data sets between frames and ensures that the receiver sees at least two of k28.5 sets (the fabric is allowed to drop one). figure 2 shows the timing characteristics of the data realignment. systems that do not require framed data can disable byte alignment by tying syncen low. when a synchronization character is detected the sync signal is asserted high and is aligned with the k28.5 character. the duration of the sync-signal pulse is equal to the duration of the data which is half an rclk period. rbc0 rbc1 sync serial rx data stream din_rxp ? din_rxn k28.5 dxx.x dxx.x dxx.x k28.5 dxx.x rd0 ? rd9 k28.5 dxx.x dxx.x dxx.x dxx.x k28.5 20 bit times (max) typical receive path latency = 18 ns dxx.x dxx.x dxx.x worst case misaligned k28.5 corrupted data misalignment corrected 10 bit times 10 bit times dxx.x k28.5 k28.5 dxx.x k28.5 figure 2. word realignment timing characteristics waveforms data reception latency the serial-to-parallel data latency is the time from when the first bit arrives at the receiver until it is output in the aligned parallel word with rd0 received as first bit. the receive latency is typically 18 ns.
slls367d ? june 1999 ? revised august 2007 9 post office box 655303 ? dallas, texas 75265 loop-back testing the transceiver can provide a self-test function by enabling (loopen to high level) the internal loop-back path. enabling loopen causes serially transmitted data to be routed internally to the receiver. the parallel data output can be compared to the parallel input data for functional verification. the external differential output is held in a static state during loop-back testing. absolute maximum ratings ? supply voltage, v cc (see note 2) ?0.5 to 4.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage, v i (ttl, pecl) ?0.5 to 4.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output current i o , (ttl) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output current i o , (pecl) ?50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range at any terminal ?0.5 to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . electrostatic discharge, 5-v tolerant input terminals (see note 3) class 1, a:1 kv, b:150 v . . . . . . . . . . . . . . electrostatic discharge, all other terminals (see note 3) class 1, a:2 kv, b:200 v . . . . . . . . . . . . . . . . . . . . . . characterized free-air operating temperature range 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature ?65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 2. all voltage values, except differential i/o bus voltages, are with respect to network ground. 3. this parameter is tested in accordance with mil-prf-38535. recommended operating conditions parameter test conditions min nom max unit supply voltage, v cc 3.14 3.3 3.47 v supply current, i cc (static) static pattern ? 180 260 ma power dissipation, p d (static) outputs open, static pattern ? 590 900 mw supply current, i cc (dynamic) k28.5 240 330 ma power dissipation, p d (dynamic) outputs open, k28.5 790 1150 mw operating free-air temperature, t a 0 70 c ? power (static pattern) = 125 mhz to the receiver and 5 ones and 5 zeros to the transmitter. reference clock (refclk) timing requirements over recommended operating conditions (unless otherwise noted) ? parameter test conditions min nom max unit frequency typ ? 0.01% 125 typ + 0.01% mhz accuracy ?100 100 ppm duty cycle 40% 50% 60% jitter random and deterministic 40 ps ? this clock should be crystal referenced to meet the requirements of the this table. the maximum rate of frequency change specified i s valid after 10 seconds from power on.
slls367d ? june 1999 ? revised august 2007 10 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating conditions (unless otherwise noted) ttl signals: td0 .. td9, refclk, loopen, syncen, sync, rd0 .. rd9, rbc0, rbc1, lckrefn parameter test conditions min typ max unit v oh high-level output voltage v cc = min, i oh = ? 400 a 2.4 3 v v ol low-level output voltage v cc = min, i ol = 1 ma 0.25 0.4 v v ih high-level input voltage 2 5.5 v v il low-level input voltage 0.8 v i ih high-level input current v cc = max, v i = 2.4 v 40 a i ih high-level input current refclk v cc = max, v i = 2.4 v 900 a i il low-level input current v cc = max, v i = 0.4 v ?40 a i il low-level input current refclk v cc = max, v i = 0.4 v ?900 a c i input capacitance 4 pf
slls367d ? june 1999 ? revised august 2007 11 post office box 655303 ? dallas, texas 75265 transmitter section differential electrical characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit ? v od ? p driver differential output voltage (peak) ( ? t x p ? t x n ? ) r l = 75 ? , see figure 3 550 1100 mv ? v od ? p driver differential output voltage (peak) ( ? t x p ? t x n ? ) r l = 50 ? , see figure 3 550 1100 mv v oc driver common-mode output voltage r l = 75 ? 2100 mv differential switching characteristics over recommended operating conditions (unless otherwise noted). parameter test conditions min typ max unit serial data deterministic jitter (peak-to-peak) differential output jitter 80 ps serial data total jitter (peak-to-peak) differential output jitter 192 ps t r3 differential signal rise time (20% to 80%) r l = 75 ? , see figure 3 c l = 5 pf, 300 ps t f3 differential signal fall time (20% to 80%) r l = 75 , see figure 3 c l = 5 pf, 300 ps 50% 20% 80% v cc ? 0.7 v v cc ? 1.6 v t f t r tx+ 50% 20% 80% v cc ? 0.7 v v cc ? 1.6 v t r t f tx? 20% 80% t f3 t r3 v od |v od | p 0 v figure 3. differential and common-mode output voltage definitions
slls367d ? june 1999 ? revised august 2007 12 post office box 655303 ? dallas, texas 75265 transmitter timing requirements over recommended operating conditions (unless otherwise noted) test conditions min nom max unit t su1 setup time, td0 ? td9 valid to refclk see figure 4 2 ns t h1 hold time, refclk to td0 ? td9 invalid see figure 4 1 ns parallel-to-serial data latency 9 ns transmit interface timing the transmit interface is defined in the 10 b spec as the 10-bit parallel data input to the physical layer for serial transmission. the timing values are specified from refclk midpoint to valid input signal levels or from valid input signal levels to refclk midpoint. td0 ? td9
slls367d ? june 1999 ? revised august 2007 13 post office box 655303 ? dallas, texas 75265 receiver section differential electrical characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit |v id | p receive input voltage (peak) ( ? r x p ? r x n ? ) see figure 5 200 1300 mv receiver and phase-locked loop performance characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit ? jitter tolerance see p802.3z specification 74.9% ui from power up at 2 nf capacitor value 500 s data acquisition lock time from power up at 0.1 f capacitor value (see note 4) 10 ms data relock time from synchronization loss 2500 ns ? ui is the unit interval of a single bit (800 ps). note 4: a filter capacitor value of 0.1 f can be used with the following consideration: the tracking bandwidth of the pll will be reduced due to the larger filter capacitor. this reduces the transmit and receive pll?s ability to reject low-frequency noise or wonder in the voltage supply or datastream. care must be taken in the filtering of the supply v cc _tx (terminal 18) and v cc _rx (terminal 50) to reject power supply noise. receive clock timing requirements over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit f clk clock frequency, rbc0 62.5 mhz f clk clock frequency, rbc1 (180 deg out of phase with rbc0) 62.5 mhz t r4 data rise time see figure 6 0.7 4 ns t f4 data fall time see figure 6 0.7 4 ns t r5 rise time, single-ended output signal on rbc0 or rbc1 see figure 6 0.7 2 ns t f5 fall time, single-ended output signal on rbc0 or rbc1 see figure 6 0.7 2 ns duty cycle, rbc0 or rbc1 40% 60% t (skew) skew time, rbc1 to rbc0 see figure 7 7.5 8 8.5 ns t su2 setup time, rd0 ? rd9, sync valid to rbc0 see figure 7 2.5 ns t su3 setup time, rd0 ? rd9, sync valid to rbc1 see figure 7 2.5 ns t su4 setup time, rbc1 to rd0 ? rd9, sync invalid see figure 7 1.5 ns t su5 setup time, rbc1 to rd0 ? rd9, sync invalid see figure 7 1.5 ns serial-to-parallel data latency 18 ns ? t (drift) is the minimum time for rbc0 or rbc1 to drift from 63.5 mhz to 64.5 mhz or from 60 mhz to 59 mhz from the rclk lock value. thi s is applicable under all input signal conditions with pll locked to the refclk of data signals. |v id | 0 v |v id | p figure 5. differential input voltage (peak-to-peak) timing waveform
slls367d ? june 1999 ? revised august 2007 14 post office box 655303 ? dallas, texas 75265 clock 50% 20% 80% t f4 t r4 data 50% 20% 80% t f5 t r5 figure 6. receiver data measurement levels rd0 ? rd9, sync
slls367d ? june 1999 ? revised august 2007 15 post office box 655303 ? dallas, texas 75265 application information host protocol device td0 ? td9 10 / refclk lckrefn loopen syncen sync rd0 ? rd9 rbc0,rbc1 rc1 rc0 dout_txp dout_txn din_rxp din_rxn tc1 tc0 v cc _tx v cc _rx controlled impedance transmission line controlled impedance transmission line controlled impedance transmission line controlled impedance transmission line pll filter capacitor = 2 nf or 0.1 f (see note c) pll filter capacitor = 2 nf or 0.1 f (see note c) tnete2201b 3.3 v 3.3 v 10 / 2 / 50 18 22 27 19 24 47 31,30 62 61 54 52 49 48 16 17 gnd_rx gnd_tx 51 15 ferrite bead ferrite bead 0.01 f 0.01 f r (pd) (see note a) 5 ? at 100 mhz 50 ? ? 75 ? v t (see note b) notes: a. r(pd) ? this value is set to match the falling edge to rising edge transistion times, typically 150 ? . to 220 ? .. b. v t (termination voltage): v t = v cc ? 1.3 v, if ac coupled v t = v cc ? 2 v, if directly coupled. c. a filter capacitor value of 0.1 f can be used with the following consideration: the tracking bandwidth of the pll will be reduced due to the larger filter capacitor. this reduces the transmit and receive pll?s ability to reject low-frequency noise or wonder in the voltage supply or datastream. care must be taken in the filtering of the supply v cc _tx (terminal 18) and v cc _rx (terminal 50) to reject power supply noise. figure 8. typical application circuit
slls367d ? june 1999 ? revised august 2007 16 post office box 655303 ? dallas, texas 75265 mechanical information the tnete2201b incorporates the latest development in ti?s package line. the new patent-pending design, designated the pwp, delivers thermal performance comparing to a heat-spreader design in a true low-profile package. the pwp for the tnete2201b is designed to maximize heat transfer away from the die through the top of the chip. as seen in figures 9 and 10 the bottom of the leadframe is deep downset towards the top of the chip, providing a thermal path away from the die and board. all this has been accomplished without exceeding the 1.15 mm height of the tqfp. this package in the 10mm 10mm tqfp (pjd) provides a thermal resistance r ja of 40 c/w and the package in the 14mm 14mm tqfp (phd) provides a r ja of 40 c/w. figure 9. heat-spreader design figure 10. leadframe downset
package option addendum www.ti.com 10-jun-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tnete2201bphd active htqfp phd 64 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr 0 to 70 tnete2201b tnete2201bpjd active htqfp pjd 64 160 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr 0 to 70 tnete2201b tnete2201bpjdr active htqfp pjd 64 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr tnete2201b tnete2201bpjdrg4 active htqfp pjd 64 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr tnete2201b tnete2201bpjw active htqfp pjw 64 160 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr 0 to 70 tnete2201b TNETE2201BPJWG4 active htqfp pjw 64 160 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr 0 to 70 tnete2201b tnete2201bpjwr active htqfp pjw 64 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr 0 to 70 tnete2201b tnete2201bpjwrg4 active htqfp pjw 64 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr 0 to 70 tnete2201b (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature.
package option addendum www.ti.com 10-jun-2014 addendum-page 2 (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tnete2201bpjdr htqfp pjd 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 q2 tnete2201bpjwr htqfp pjw 64 1000 330.0 24.4 13.7 13.7 1.6 16.0 24.0 q2 package materials information www.ti.com 14-jul-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tnete2201bpjdr htqfp pjd 64 1000 367.0 367.0 45.0 tnete2201bpjwr htqfp pjw 64 1000 367.0 367.0 45.0 package materials information www.ti.com 14-jul-2012 pack materials-page 2

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